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? semiconductor components industries, llc, 2003 december, 2003 ? rev. 6 1 publication order number: mc44608/d mc44608 few external components reliable and flexible smps controller the mc44608 is a high performance voltage mode controller designed for off?line converters. this high voltage circuit that integrates the start?up current source and the oscillator capacitor, requires few external components while offering a high flexibility and reliability. the device also features a very high efficiency stand?by management consisting of an effective pulsed mode operation. this technique enables the reduction of the stand?by power consumption to approximately 1.0 w while delivering 300 mw in a 150 w smps. ? integrated start?up current source ? lossless off?line start?up ? direct off?line operation ? fast start?up general features ? flexibility ? duty cycle control ? undervoltage lockout with hysteresis ? on chip oscillator switching frequency 40, 75, or 100 khz ? secondary control with few external components protections ? maximum duty cycle limitation ? cycle by cycle current limitation ? demagnetization (zero current detection) protection ? aover v cc protectiono against open loop ? programmable low inertia over voltage protection against open loop ? internal thermal protection smps controller ? pulsed mode techniques for a very high efficiency low power mode ? lossless startup ? low dv/dt for low emi radiations device switching frequency shipping ordering information mc44608p40 40 khz mc44608p75 75 khz pdip?8 p suffix case 626 1 8 1 8 7 6 5 2 3 4 (top view) demag i sense control input v i pin connections and marking diagram gnd v cc driver 44608pxxx package plastic dip?8 plastic dip?8 50/rail 50/rail awl yyww awl = manufacturing code yyww = date code (top view) MC44608P100 100 khz plastic dip?8 50/rail http://onsemi.com
mc44608 http://onsemi.com 2 + - + - + - dmg demag logic output start-up phase switching phase latched off phase 1 v 4 khz filter regulation block switching phase s2 s3 & latched off phase stand-by thermal dmg out disable ovp uvlo1 switching phase start-up phase latched off phase uvlo2 9 ma start-up cc buffer pwm q r s & & pwm vpwm & osc osc clock stand-by leading edge s1 10 & stand-by 18 6 5 4 3 2 demag vi isense control gnd driver v input cc shutdown latch uvlo2 management v & source management enable blanking output cs 2 s >120 a >24 a 50 mv /20 mv noc oc 200 a start-up phase figure 1. representative block diagram maximum ratings rating symbol value unit total power supply current i cc 30 ma output supply voltage with respect to ground v cc 16 v all inputs except vi v inputs ?1.0 to +16 v line voltage absolute rating v i 500 v recommended line voltage operating condition v i 400 v power dissipation and thermal characteristics maximum power dissipation at t a = 85 c p d 600 mw thermal resistance, junction?to?air r ja 100 c/w operating junction temperature t j 150 c operating ambient temperature t a ?25 to +85 c
mc44608 http://onsemi.com 3 electrical characteristics characteristic symbol min typ max unit output section output resistor sink resistance r ol 5.0 8.5 15 source resistance r oh ? 15 ? output voltage rise time (from 3.0 v up to 9.0 v) (note 1) t r ? 50 ? ns output voltage falling edge slew?rate (from 9.0 v down to 3.0 v) (note 1) t f ? 50 ? ns control input section duty cycle @ i pin3 = 2.5 ma d 2ma ? ? 2.0 % duty cycle @ i pin3 = 1.0 ma d 1ma 36 43 48 % control input clamp voltage (switching phase) @ i pin3 = ?1.0 ma 4.75 5.0 5.25 v latched phase control input voltage (stand?by) @ i pin3 = +500 a v lp?stby 3.4 3.9 4.3 v latched phase control input voltage (stand?by) @ i pin3 = +1.0 ma v lp?stby 2.4 3.0 3.7 v current sense section maximum current sense input threshold v cs?th 0.95 1.0 1.05 v input bias current i b?cs ?1.8 ? 1.8 a stand?by current sense input current i cs?stby 180 200 220 a start?up phase current sense input current i cs?stup 180 200 220 a propagation delay (current sense input to output @ v th t mos = 3.0 v) t plh(in/out) ? 220 ? ns leading edge blanking duration mc44608p40 t leb ? 480 ? ns leading edge blanking duration mc44608p75 t leb ? 250 ? ns leading edge blanking duration MC44608P100 t leb ? 200 ? ns leading edge blanking + propagation delay mc44608p40 t dly 500 680 900 ns leading edge blanking + propagation delay mc44608p75 t dly 370 470 570 ns leading edge blanking + propagation delay MC44608P100 t dly 300 420 500 ns oscillator section normal operation frequency mc44608p40 f osc 36 40 44 khz normal operation frequency mc44608p75 f osc 68 75 82 khz normal operation frequency MC44608P100 f osc 90 100 110 khz maximum duty cycle @ f = f osc d max 78 82 86 % overvoltage section quick ovp input filtering (r demag = 100 k ) t filt ? 250 ? ns propagation delay (i demag > i ovp to output low) t phl(in/out) ? 2.0 ? s quick ovp current threshold i ovp 105 120 140 a protection threshold level on v cc v cc?ovp 14.8 15.3 15.8 v minimum gap between v cc?ovp and v stup?th v cc?ovp ? v stup 1.0 ? ? v 1. this parameter is measured using 1.0 nf connected between the output and the ground.
mc44608 http://onsemi.com 4 electrical characteristics (v cc = 12 v, for typical values t a = 25 c, for min/max values t a = ?25 c to +85 c unless otherwise noted) (note 2) characteristic symbol min typ max unit demagnetization detection section (note 3) demag comparator threshold (v pin1 increasing) v dmg?th 30 50 69 mv demag comparator hysteresis (note 4) h dmg ? 30 ? mv propagation delay (input to output, low to high) t phl(in/out) ? 300 ? ns input bias current (v demag = 50 mv) i dem?lb ?0.6 ? ? a negative clamp level (i demag = ?1.0 ma) v cl?neg?dem ?0.9 ?0.7 ?0.4 v positive clamp level @ i demag = 125 a v cl?pos? dem?h 2.05 2.3 2.8 v positive clamp level @ i demag = 25 a v cl?pos? dem?l 1.4 1.7 1.9 v overtemperature section trip level over temperature t high ? 160 ? c hysteresis t hyst ? 30 ? c stand?by maximum current reduction section normal mode recovery demag pin current threshold i dem?nm 20 25 30 a k factors section for pulsed mode operation i ccs / i stup mc44608p40 10 x k1 2.4 2.9 3.8 ? i ccs / i stup mc44608p75 10 x k1 2.8 3.3 4.2 ? i ccs / i stup MC44608P100 10 x k1 3.1 7.0 4.5 ? i ccl / i stup 10 3 x k2 46 52 63 ? (v stup ? uvlo2) / (v stup ? uvlo1) 10 2 x k sstup 1.8 2.2 2.6 ? (uvlo1 ? uvlo2) / (v stup ? uvlo1) 10 2 x k sl 90 120 150 ? i cs / v csth 10 6 x y cstby 175 198 225 ? demag ratio i ovp / i dem nm dmgr 3.0 4.7 5.5 ? (v3 1.0 ma ? v3 0.5 ma ) / (1.0 ma ? 0.5 ma) r3 ? 1800 ? v control latch?off v3 ? 4.8 ? v supply section minimum start?up voltage v ilow ? ? 50 v v cc start?up voltage v stup?th 12.5 13.1 13.8 v output disabling v cc voltage after turn on v uvlo1 9.5 10 10.5 v hysteresis (v stup?th ? v uvlo1 ) h stup?uvlo1 ? 3.1 ? v v cc undervoltage lockout voltage v uvlo2 6.2 6.6 7.0 v hysteresis (v uvlo1 ? v uvlo2 ) h uvlo1?uvlo2 ? 3.4 ? v absolute normal condition v cc start current @ (v i = 100 v) and (v cc = 9.0 v) ?(i cc ) 7.0 9.5 12.8 ma switching phase supply current (no load) mc44608p40 mc44608p75 MC44608P100 i ccs 2.0 2.4 2.6 2.6 3.2 3.4 3.6 4.0 4.5 ma latched off phase supply current i cc?latch 0.3 0.5 0.68 ma hiccup mode duty cycle (no load) hiccup ? 10 ? % 2. adjust v cc above the start?up threshold before setting to 12 v. low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. 3. this function can be inhibited by connecting pin 1 to gnd. 4. guaranteed by design (non tested).
mc44608 http://onsemi.com 5 pin function description pin name description 1 demag the demag pin offers 3 different functions: zero voltage crossing detection (50 mv), 24 a current detection and 120 a current detection. the 24 a level is used to detect the secondary reconfiguration status and the 120 a level to detect an over voltage status called quick ovp. 2 i sense the current sense pin senses the voltage developed on the series resistor inserted in the source of the power mosfet. when i sense reaches 1.0 v, the driver output (pin 5) is disabled. this is known as the over current protection function. a 200 a current source is flowing out of the pin 3 during the start?up phase and during the switching phase in case of the pulsed mode of operation. a resistor can be inserted between the sense resistor and the pin 2, thus a programmable peak current detection can be performed during the smps stand?by mode. 3 control input a feedback current from the secondary side of the smps via the opto?coupler is injected into this pin. a resistor can be connected between this pin and gnd to allow the programming of the burst duty cycle during the stand?by mode. 4 ground this pin is the ground of the primary side of the smps. 5 driver the current and slew rate capability of this pin are suited to drive power mosfets. 6 v cc this pin is the positive supply of the ic. the driver output gets disabled when the voltage becomes higher than 15 v and the operating range is between 6.6 v and 13 v. an intermediate voltage level of 10 v creates a disabling condition called latched off phase. 7 this pin is to provide isolation between the v i pin 8 and the v cc pin 6. 8 v i this pin can be directly connected to a 500 v voltage source for start?up function of the ic. during the start?up phase a 9.0 ma current source is internally delivered to the v cc pin 6 allowing a rapid charge of the v cc capacitor. as soon as the ic starts?up, this current source is disabled. operating description regulation figure 2. regulator s3 10 & 3 regulation 20 s2 10 control input v cc v lp-stby 5 v 4 khz filter output v dd pwm comparator switching phase stand-by latched off phase 1.6 v the pin 3 senses the feedback current provided by the opto coupler. during the switching phase the switch s2 is closed and the shunt regulator is accessible by the pin 3. the shunt regulator voltage is typically 5.0 v. the dynamic resistance of the shunt regulator represented by the zener diode is 20 . the gain of the control input is given on figure 11 which shows the duty cycle as a function of the current injected into the pin 3. a 4.0 khz filter network is inserted between the shunt regulator and the pwm comparator to cancel the high frequency residual noise. the switch s3 is closed in stand?by mode during the latched off phase while the switch s2 remains open. (see section pulsed mode duty cycle control). the resistor rdpulsed (rduty cycle burst) has no effect on the regulation process. this resistor is used to determine the burst duty cycle described in the chapter apulsed duty cycle controlo on page 8. pwm latch the mc44608 works in voltage mode. the on?time is controlled by the pwm comparator that compares the oscillator sawtooth with the regulation block output (refer to the block diagram on page 2). the pwm latch is initialized by the oscillator and is reset by the pwm comparator or by the current sense comparator in case of an over current. this configuration ensures that only a single pulse appears at the circuit output during an oscillator cycle. current sense the inductor current is converted to a positive voltage by inserting a ground reference sense resistor r sense in series with the power switch. the maximum current sense threshold is fixed at 1.0 v. the peak current is given by the following equation: ipk max 1 r sense ( ) (a)
mc44608 http://onsemi.com 6 in stand?by mode, this current can be lowered as due to the activation of a 200 a current source: ipk max stby 1 (r cs (k ) 0, 2) r sense ( ) (a) figure 3. current sense + - switching phase 1 v stand-by 10 & 2 isense l.e.b. overcurrent oc 200 a start-up comparator rcs rsense the current sense input consists of a filter (6.0 k , 4.0 pf) and of a leading edge blanking. thanks to that, this pin is not sensitive to the power switch turn on noise and spikes and practically in most applications, no filtering network is required to sense the current. finally, this pin is used: ? as a protection against over currents (isense > i) ? as a reduction of the peak current during a pulsed mode switching phase. the overcurrent propagation delay is reduced by producing a sharp output turn off (high slew rate). this results in an abrupt output turn off in the event of an over current and in the majority of the pulsed mode switching sequence. demagnetization section the mc44608 demagnetization detection consists of a comparator designed to compare the v cc winding voltage to a reference that is typically equal to 50 mv. this reference is chosen low to increase effectiveness of the demagnetization detection even during start?up. a latch is incorporated to turn the demagnetization block output into a low level as soon as a voltage less than 50 mv is detected, and to keep it in this state until a new pulse is generated on the output. this avoids any ringing on the input signal which may alter the demagnetization detection. for a higher safety, the demagnetization block output is also directly connected to the output, which is disabled during the demagnetization phase. the demagnetization pin is also used for the quick, programmable ovp. in fact, the demagnetization input current is sensed so that the circuit output is latched off when this current is detected as higher than 120 a. figure 4. demagnetization block & 1 dmg > 24 a output current mirror oscillator buffer + - idemag idemag 50/20 mv >120 a demag rq s dmg this function can be inhibited by grounding it but in this case, the quick and programmable ovp is also disabled. oscillator the mc44608 contains a fixed frequency oscillator. it is built around a fixed value capacitor ct successively charged and discharged by two distinct current sources ich and idch. the window comparator senses the ct voltage value and activates the sources when the voltage is reaching the 2.4 v/4.0 v levels. figure 5. oscillator block + - from demag 4 v 2.4 v & window osc ich comp dmg sdch idch logic block sch clock ct the complete demagnetization status dmg is used to inhibit the recharge of the ct capacitor. thus in case of incomplete transformer demagnetization the next switching cycle is postpone until the dmg signal appears. the oscillator remains at 2.4 v corresponding to the sawtooth valley voltage. in this way the smps is working in the so called sops mode (self oscillating power supply). in that case the effective switching frequency is variable and no longer depends on the oscillator timing but on the external working conditions (refer to dmg signal in the figure 6).
mc44608 http://onsemi.com 7 figure 6. vcont 2.4 v iprim dmg clock osc 4 v the osc and clock signals are provided according to the figure 6. the clock signals correspond to the ct capacitor discharge. the bottom curve represents the current flowing in the sense resistor rcs. it starts from zero and stops when the sawtooth value is equal to the control voltage vcont. in this way the smps is regulated with a voltage mode control. overvoltage protection the mc44608 offers two ovp functions: ? a fixed function that detects when v cc is higher than 15.4 v ? a programmable function that uses the demag pin. the current flowing into the demag pin is mirrored and compared to the reference current iovp (120 a). thus this ovp is quicker as it is not impacted by the v cc inertia and is called qovp. in both cases, once an ovp condition is detected, the output is latched off until a new circuit start?up. start?up management the v i pin 8 is directly connected to the hv dc rail vin. this high voltage current source is internally connected to the v cc pin and thus is used to charge the v cc capacitor. the v cc capacitor charge period corresponds to the start?up phase. when the v cc voltage reaches 13 v, the high voltage 9.0 ma current source is disabled and the device starts working. the device enters into the switching phase. it is to be noticed that the maximum rating of the v i pin 8 is 500 v. esd protection circuitry is not currently added to this pin due to size limitations and technology constraints. protection is limited by the drain?substrate junction in avalanche breakdown. to help increase the application safety against high voltage spike on that pin it is possible to insert a small wattage 1.0 k series resistor between the v in rail and pin 8. the figure 7 shows the v cc voltage evolution in case of no external current source providing current into the v cc pin during the switching phase. this case can be encountered in smps when the self supply through an auxiliary winding is not present (strong overload on the smps output for example). the figure 17 also depicts this working configuration. figure 7. hiccup mode start-up latched off phase switching phase phase v cc 6.5 v 10 v 13 v in case of the hiccup mode, the duty cycle of the switching phase is in the range of 10%. mode transition the lw latch figure 8 is the memory of the working status at the end of every switching sequence. two different cases must be considered for the logic at the termination of the switching phase: 1. no over current was observed 2. an over current was observed these 2 cases are corresponding to the signal labelled noc in case of ano over currento and aoco in case of over current. so the effective working status at the end of the on time memorized in lw corresponds to q=1 for no over current and q=0 for over current. this sequence is repeated during the switching phase. several events can occur: 1. smps switch off 2. smps output overload 3. transition from normal to pulsed mode 4. transition from pulsed mode to normal mode figure 8. transition logic & i sq r lw + - & cs q & r2 q s mode leb out 1 v vpwm out stand-by r1 start-up phase switching phase start-up phase noc oc > 24 a latched off phase & demag s1 switch ? 1. smps switch off when the mains is switched off, so long as the bulk electrolithic bulk capacitor provides energy to the smps, the controller remains in the switching phase. then the peak current reaches its maximum peak value, the switching frequency decreases and all the secondary voltages are reduced. the v cc voltage is also reduced. when v cc is equal to 10 v, the smps stops working.
mc44608 http://onsemi.com 8 ? 2. overload in the hiccup mode the 3 distinct phases are described as follows (refer to figure 7): the switching phase: the smps output is low and the regulation block reacts by increasing the on time (dmax = 80%). the oc is reached at the end of every switching cycle. the lw latch (figure 8) is reset before the vpwm signal appears. the smps output voltage is low. the v cc voltage cannot be maintained at a normal level as the auxiliary winding provides a voltage which is also reduced in a ratio similar to the one on the output (i.e. vout nominal / vout short?circuit). consequently the v cc voltage is reduced at an operating rate given by the combination v cc capacitor value together with the i cc working consumption (3.2 ma) according to the equation 2. when v cc crosses 10v the working phase gets terminated. the lw latch remains in the reset status. the latched?off phase: the v cc capacitor voltage continues to drop. when it reaches 6.5 v this phase is terminated. its duration is governed by equation 3. the start?up phase is reinitiated. the high voltage start?up current source (?i cc1 = 9.0 ma) is activated and the mode latch is reset. the v cc voltage ramps up according to the equation 1. when it reaches 13 v, the ic enters into the switching phase. the next switching phase: the high voltage current source is inhibited, the mode latch (q=0) activates the normal mode of operation. figure 3 shows that no current is injected out pin 2. the over current sense level corresponds to 1.0 v. as long as the overload is present, this sequence repeats. the switching phase duty cycle is in the range of 10%. ? 3. transition from normal to pulsed mode in this sequence the secondary side is reconfigured (refer to the typical application schematic on page 13). the high voltage output value becomes lower than the normal mode regulated value. the tl431 shunt regulator is fully off. in the smps stand?by mode all the smps outputs are lowered except for the low voltage output that supply the wake?up circuit located at the isolated side of the power supply. in that mode the secondary regulation is performed by the zener diode connected in parallel to the tl431. the secondary reconfiguration status can be detected on the smps primary side by measuring the voltage level present on the auxiliary winding laux. (refer to the demagnetization section). in the reconfigured status, the laux voltage is also reduced. the v cc self?powering is no longer possible thus the smps enters in a hiccup mode similar to the one described under the overload condition. in the smps stand?by mode the 3 distinct phases are: the switching phase: similar to the overload mode. the current sense clamping level is reduced according to the equation of the current sense section, page 5. the c.s. clamping level depends on the power to be delivered to the load during the smps stand?by mode. every switching sequence on/off is terminated by an oc as long as the secondary zener diode voltage has not been reached. when the zener voltage is reached the on cycle is terminated by a true pwm action. the proper switching phase termination must correspond to a noc condition. the lw latch stores this noc status. the latched off phase: the mode latch is set. the start?up phase is similar to the overload mode. the mode latch remains in its set status (q=1). the switching phase: the stand?by signal is validated and the 200 a is sourced out of the current sense pin 2. ? 4. transition from stand?by to normal the secondary reconfiguration is removed. the regulation on the low voltage secondary rail can no longer be achieved, thus at the end of the switching phase, no pwm condition can be encountered. the lw latch is reset. at the next working phase a normal mode status takes place. in order to become independent of the recovery time constant on the secondary side of the smps an additional reset input r2 is provided on the mode latch. the condition idemag<24 a corresponds to the activation of the secondary reconfiguration status. the r2 reset insures a direct return into the normal mode. pulsed mode duty cycle control during the sleep mode of the smps the switch s3 is closed and the control input pin 3 is connected to a 4.6 v voltage source thru a 500 resistor. the discharge rate of the v cc capacitor is given by i cc?latch (device consumption during the la tched off phase) in addition to the current drawn out of the pin 3. connecting a resistor between the pin 3 and gnd (r dpulsed ) a programmable current is drawn from the v cc through pin 3. the duration of the latched off phase is impacted by the presence of the resistor r dpulsed . the equation 3 shows the relation to the pin 3 current. pulsed mode phases equations 1 through 8 define and predict the effective behavior during the pulsed mode operation. the equations 6, 7, and 8 contain k, y, and d factors. these factors are combinations of measured parameters. they appear in the parameter section akfactors for pulsed mode operationo page 4. in equations 3 through 8 the pin 3 current is the current defined in the above section apulsed mode duty cycle controlo.
mc44608 http://onsemi.com 9 equation 1 start?up phase duration: t startup c vcc (v stup uvlo2) i stup where: i stup is the start?up current flowing through v cc pin c vcc is the v cc capacitor value equation 2 switching phase duration: t switch c vcc (v stup uvlo1) i ccs i g where: i ccs is the no load circuit consumption in switching phase i g is the current consumed by the power switch equation 3 latched?off phase duration: t latched off c vcc (uvlo1 uvlo2) i ccl i pin3 where: i ccl is the latched off phase consumption i pin3 is the current drawn from pin3 adding a resistor equation 4 burst mode duty cycle: d bm t switch t start up t switch t latched off equation 5 d bm c vcc (v stup uvlo1) i ccs i g c vcc (v stup uvlo2) i stup c vcc (v stup uvlo1) i ccs i g c vcc (uvlo1 uvlo2) i ccl i pin3 equation 6 d bm 1 1 k s stup i ccs i g i stup k s l i ccs i g i ccl i pin3 where: k s/stup = (v stup ? uvlo2)/(v stup ? uvlo1) k s/l = (uvlo1 ? uvlo2)/(v stup ? uvlo1)
mc44608 http://onsemi.com 10 equation 7 d bm 1 1
i ccs i g i stup k s stup k s l i stup i ccl i pin3 equation 8 d bm 1 1
k1 i g i stup
k s stup (k s l 1 k2 i pin3 i stup ) where: k1 = i ccs /i stup k2 = i ccl/ i stup k s/stup = (v stup ?uvlo2)/(v stup ?uvlo1) k s/l = (uvlo1?uvlo2)/(v stup ?uvlo1) pulsed mode current sense clamping level equations 9, 10, 11 and 12 allow the calculation of the rcs value for the desired maximum current peak value during the smps stand?by mode. equation 9 ipk stby v csth (r cs i cs ) r s where: v cs?th is the cs comparator threshold i cs is the cs internal current source r s is the sensing resistor r cs is the resistor connected between pin 2 and r s equation 10 ipk stby v csth 1 r cs i cs v csth r s equation 11 ipk stby v csth 1 (r cs y csstby ) r s where: y cs?stby = i cs /v cs?th taking into account the circuit propagation delay ( t cs ) and the power switch reaction time ( t ps ): equation 12 ipk stby v csth 1 (r cs y csstby ) r s v in ( t cs t ps ) l p
mc44608 http://onsemi.com 11 figure 9. output switching speed 10 time (ns) 20 30 40 50 60 10 11 12 13 14 15 t_fall t_rise pin6 v cc voltage (v) figure 10. frequency stability 65.0 frequency 67.0 71.0 75.0 77.0 79.0 10 11 12 13 14 15 v cc voltage (v) 73.0 69.0 -25 c 25 c 85 c figure 11. duty cycle control 0 switching duty cycle (%) 10 40 60 70 80 0.0 0.5 1.0 1.5 2.0 2.5 current injected in pin3 (ma) 50 20 -25 c 25 c 85 c 90 30 4.98 vpin3 (v) 0.5 1.5 2 2.5 current injected in pin 3 (ma) 1 4.99 5.00 5.01 5.02 5.03 5.04 5.05 5.06 5.07 5.08 -25 c 25 c 85 c figure 12. vpin3 during the working period 1.5 vpin3 voltage (v) -1.6 current injected in pin 3 (ma) -25 c 25 c 85 c -1.4 -1.2 -1.0 -.08 -.06 -.04 -.02 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 figure 13. vpin3 during the latched off period figure 14. device consumption when switching 3.00 pin6 current (ma) 3.20 3.80 4.20 4.40 4.60 10 11 12 13 14 15 pin6 v cc voltage (v) 4.00 3.40 -25 c 25 c 85 c 4.80 3.60
mc44608 http://onsemi.com 12 5.00 -icc (ma) 6.00 7.00 8.00 10.00 11.00 0 100 200 300 400 500 vi pin8 voltage (vi) -25 c 25 c 85 c 9.00 figure 15. high voltage current source 5.00 switching duty cycle (%) 6.00 7.00 8.00 11.00 0 100 200 300 400 500 vi pin voltage (v) -25 c 25 c 85 c 9.00 figure 16. overload burst mode 10.00 12.00 figure 17. hiccup mode waveforms the data in figure 16 corresponds to the waveform in figure 17. the figure 17 shows v cc , i cc , i sense (pin 2) and v out (pin 5). v out (pin 5) in fact shows the envelope of the output switching pulses. this mode corresponds to an overload condition.
mc44608 http://onsemi.com 13 the figure 19 represents a complete power supply using the secondary reconfiguration. the specification is as follows: input source: 85 vac to 265 vac 3 outputs 112 v/0.45 a 16 v/1.5 a 8.0 v/1.0 a output power 80 w stand?by mode @ pout = 300 mw, 1.3 w figure 18. typical application + + + + 22 f + i 8 7 6 5 1 2 3 4 rfi filter 2n2fy 4.7 k 47 k 1n4934 120 pf mc44608p75 r10 10 k r9 100 k r8 2.4 k r12 1 k c18 100 nf c19 33 nf r11 4.7 k mtp6n60e d7 1n4148 r5 100 k c7 16 v v cc r21 47 r3 0.27 opt1 c8 100 nf r4 3.9 k d13 1n4148 post reg. p off on on = normal mode off = pulsed mode d14 mr856 r17 2.2 k 5 w c9 470 pf 630 v 8 9 r19 18 k 11 10 14 12 c16 120 pf d10 mr852 c14 1000 f 35 v d9 mr852 c15 f 1000 16 v 3 2 1 3 2 1 c17 d12 r7 c12 f 47 250 v c13 100 nf d18 mr856 220 pf 500 v c11 c20 c3 1 nf c4 1 nf d1, d2, d3, d4 1n5404 r1 22 k 5 w c5 220 f 400 v c6 47 nf 630 v d6 mr856 sense 6 7 1 2 fi c1 100 nf wide mains 47288900 r f6 d5 1n4007 j4 j3 8 v/1 a 16 v/1.5 a 112 v/0.45 a 4 kv r16 mcr22-6 dz1 dz3 10 v dz2 tl431clp r2 10
mc44608 http://onsemi.com 14 the secondary reconfiguration is activated by the p through the switch. the dv/dt appearing on the high voltage winding (pins 14 of the transformer) at every tmos switch off, produces a current spike through the series rc network r7, c17. according to the switch position this spike is either absorbed by the ground (switch closed) or flows into the thyristor gate (switch open) thus firing the mcr22?6. the closed position of the switch corresponds to the pulsed mode activation. in this secondary side smps status the high voltage winding (12?14) is connected through d12 and dz1 to the 8.0 v low voltage secondary rail. the voltages applied to the secondary windings 12?14, 10?11 and 6?7 (vaux) are thus divided by ratio n12?14 / n9?8 (number of turns of the winding 12?14 over number of turns of the winding 9?8). in this reconfigured status all the secondary voltages are lowered except the 8.0 v one. the regulation during every pulsed or burst is performed by the zener diode dz3 which value has to be chosen higher than the normal mode regulation level. this working mode creates a voltage ripple on the 8.0 v rail which generally must be post regulated for the microprocessor supply. figure 19. smps pulsed mode the figure 19 shows the smps behavior while working in the reconfigured mode. the top curve represents the v cc voltage (pin 6 of the mc44608). the middle curve represents the 8.0 v rail. the regulation is taking place at 11.68 v. on the bottom curve the pin 2 voltage is shown. this voltage represents the current sense signal. the pin 2 voltage is the result of the 200 a current source activated during the start?up phase and also during the working phase which flows through the r4 resistor. the used high resolution mode of the oscilloscope does not allow to show the effective ton current flowing in the sensing resistor r11.
mc44608 http://onsemi.com 15 package dimensions pdip?8 p suffix plastic package case 626?05 issue l notes: 1. dimension l to center of lead when formed parallel. 2. package contour optional (round or square corners). 3. dimensioning and tolerancing per ansi y14.5m, 1982. 14 5 8 f note 2 ?a? ?b? ?t? seating plane h j g d k n c l m m a m 0.13 (0.005) b m t dim min max min max inches millimeters a 9.40 10.16 0.370 0.400 b 6.10 6.60 0.240 0.260 c 3.94 4.45 0.155 0.175 d 0.38 0.51 0.015 0.020 f 1.02 1.78 0.040 0.070 g 2.54 bsc 0.100 bsc h 0.76 1.27 0.030 0.050 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m --- 10 --- 10 n 0.76 1.01 0.030 0.040
mc44608 http://onsemi.com 16 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 mc44608d the product described herein (mc44608), may be covered by one or more of the following u.s. patents: 6,208,538 b1; 6,392,906 b2 . there may be other patents pending. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.

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